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Download PRACTICAL DESIGN TECHNIQUES FOR SENSOR SIGNAL
Transcript
ADCS FOR SIGNAL CONDITIONING pipelined converters have a minimum allowable conversion rate and must be kept running to prevent saturation of internal nodes. 12-BIT TWO-STAGE PIPELINED ADC ARCHITECTURE ANALOG INPUT SHA 1 SHA 2 + _ SAMPLING CLOCK TIMING 6-BIT ADC 6-BIT DAC 6 7-BIT ADC BUFFER REGISTER 7 6 ERROR CORRECTION LOGIC 12 OUTPUT REGISTERS OUTPUT DATA 12 Figure 8.7 TYPICAL PIPELINED ADC TIMING SAMPLE X SAMPLE X+1 SAMPLE X+2 SAMPLING CLOCK OUTPUT DATA DATA X–2 DATA X–1 DATA X ABOVE SHOWS TWO CLOCK-CYCLES PIPELINE DELAY Figure 8.8 8.7
