Download Xilinx Command Line Tools User Guide

Chapter 4: NetGen
-shm (Write $shm Statements in Test Fixture File)
This option places $shm statements in the structural Verilog file created by NetGen. These $shm statements allow
NC-Verilog to display simulation data as waveforms. This option is for use with Cadence NC-Verilog files only.
Syntax
-shm
-ul (Write uselib Directive)
This option causes NetGen to write a library path pointing to the SimPrim library into the output Verilog (.v)
file. The path is written as shown below:
uselib dir=$XILINX/verilog/src/simprims libext=.v
$XILINX is the location of the Xilinx software.
If you do not enter a -ul option, the ‘uselib line is not written into the Verilog file.
Note A blank ‘uselib statement is automatically appended to the end of the Verilog file to clear out the ‘uselib
data. If you use this option, do not use the -ism option.
Note The -ul option is valid for SIMPRIM-based functional simulation and timing simulation flows; although
not all simulators support the ‘uselib directive. Xilinx recommends using this option with caution.
Syntax
-ul
-vcd (Write $dump Statements In Test Fixture File)
This option writes $dumpfile/$dumpvars statements in testfixture. This option is for use with Cadence Verilog
files only.
Syntax
-vcd
VHDL-Specific Options for Functional and Timing Simulation
This section describes the VHDL-specific command line options for timing simulation.
•
-a (Architecture Only)
•
-ar (Rename Architecture Name)
•
-extid (Extended Identifiers)
•
-rpw (Specify the Pulse Width for ROC)
•
-tpw (Specify the Pulse Width for TOC)
-a (Architecture Only)
This option suppresses generation of entities in the output. When specified, only architectures appear in the
output. By default, NetGen generates both entities and architectures for the input design.
Syntax
-a
-ar (Rename Architecture Name)
This option lets you change the architecture name generated by NetGen. The default architecture name for
each entity in the netlist is STRUCTURE.
Command Line Tools User Guide
UG628 (v 11.4) December 2, 2009
www.xilinx.com
63