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Chapter 23: XFLOW
Note This flow type supports FPGA device families only. You cannot use NCD files from previous software
releases with Modular Design in the current release. You must generate new NCD files with the current
release of the software.
Syntax
-module option_file -active module_name
This flow type invokes the fpga.flw flow file and runs NGDBuild to create an NGD file with just the specified
active module expanded. This output NGD file is named after the top-level design. XFLOW then runs MAP
and PAR to create a PIM.
Then, you must run PIMCreate to publish the PIM to the PIMs directory. PIMCreate copies the local,
implemented module file, including the NGO, NGM and NCD files, to the appropriate module directory inside
the PIMs directory and renames the files to module_name .extension. To run PIMCreate, type the following
on the command line or add it to your flow file:
pimcreate pim_directory -ncd design_name_routed.ncd
The working directory for this flow type should be the active module directory. You can either run the -module
flow type from the active module directory or use the -wd option to specify this directory. This directory should
include the active module netlist file and the top-level UCF file generated during the Initial Budgeting phase.
You must specify the name of the active module after the -active option, and use the top-level NGO file
as the input design file.
Xilinx® provides the following option files for use with this flow type. These files allow you to optimize your
design based on different parameters.
Option Files for -module Flow Type
Option Files
Description
fast_runtime.opt
Optimized for fastest runtimes at the expense of design
performance
Recommended for medium to slow speed designs
balanced.opt
Optimized for a balance between speed and high effort
high_effort.opt
Optimized for high effort at the expense of longer runtimes
Recommended for designs that operate at high speeds
Example
The following example shows how to implement a module.
xflow -p xc5vlx30ff324-2 -module balanced.opt -active controller
~teamleader/mod_des/implemented/top/top.ngo
-sta (Create a File for Static Timing Analysis)
This flow type generates a file that can be used to perform static timing analysis of an FPGA design. It invokes
the fpga.flw flow file and runs NGDBuild and NetGen to generate a Verilog netlist compatible with supported
static timing analysis tools.
Syntax
-sta option_file
Xilinx® provides the following option file for use with this flow type.
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Command Line Tools User Guide
UG628 (v 11.4) December 2, 2009