Download MPC5121e Hardware Design Guide

Display Connectors and PCB Considerations
Display Mode
Horizontal Frequency Vertical Frequency Pixel Clock
Sync Polarity
(kHz)
(Hz)
(MHz)
(Horizontal/Vertical)
1024  768
48.4
60.0
65.0
–/–
1024  768
60.0
75.0
78.8
+/+
2. Compare your maximal pixel clock frequency with the specification. Have in mind that the DIU
clock is derived from the CSB_CLK and hence depends on your clock configurations. The
DIU_CLK is maximally 1/31 of CSB_CLK (refer to the SCFR1 register description in the
MPC5121e reference manual). Since CSB_CLK is restricted to maximal 200 MHz, a maximal
pixel clock of 66.6 MHz results. If your system is configured for CSB_CLK = 150 MHz your
maximal pixel clock is 50 MHz.
3. Find a pixel clock divider to get a pixel clock as close as possible to the display specification. For
this example, assuming a CSB_CLK of 200 MHz, we set the DIU_DIV in the SCFR1 register to a
ratio of 1/3 CSB_CLK which gives us a pixel clock of 66.6 MHz (register SCFR1[DIU_DIV] =
0xC).
4. Calculate the horizontal timing parameters (refer to HSYN_PARA and VSYN_PARA register
description in the MPC5121e reference manual):
For example: 200/3 (MHz) / 48.4 (kHz/px) = 1377 px. Since the display has 1024 pixels the
resulting horizontal blanking cycle is 1377 px – 1024 px = 253 px = FP_H + PW_H + BP_H.2
5. Calculate the vertical timing parameters:
For example: (200/3 (MHz) / 1377 px) / 60 (Hz/px2) = 807 px. So the resulting vertical blanking
cycle is 807 px – 764 px = 39 px = FP_V + PW_V + BP_V.2
6. Find the synchronization polarity from the display specification. In our example it is negative for
both: DIU_VSYNC and DIU_HSYNC.
5
Display Connectors and PCB Considerations
Various possible interfaces are discussed above. Invariably cabling will need to be designed for the specific
connector that the customer has chosen. A few considerations are appropriate for performance, impedance
loading, and termination of the display interface. In display applications it is important to use cable of the
proper impedance, as well as to ensure that the cable is properly terminated.
Especially for analog signals, the connectors and the material used for cabling must be chosen such that
signal losses and noise be kept to a minimum.
The DVI and LVDS, as well as analog converters, have a special need that must be considered for
connectors. The need is the same as for the cable or PCB trace itself: to carry signals with minimum loss
and distortion.
1. In reference manual rev. 3 it is stated that the maximal divider is ½. This is an error in the manual. Further revisions will correct
this.
2. The distribution to these three register values doesn't really matter. Just be aware that PW_H/PW_V cannot be zero. Refer to
further documentation for more information about synchronization pulses.
MPC5121e DIU Hardware Interface, Rev. 0
Freescale Semiconductor
121