Download MPC5121e Hardware Design Guide

Overview
6. Send a precharge all command and thereafter wait at least tRP.
7. Send a mode register set command to enable DLL in the extended mode register and thereafter wait
at least tMRD.
8. Send a mode register set command to program the mode register with DLL reset and thereafter wait
at least 200 clock cycles.
9. Send a precharge all command and thereafter wait at least tRP.
10. Send an auto refresh command and thereafter wait at least tRP.
11. Perform step 10 again.
12. Send a mode register set command to program the mode register without DLL reset and thereafter
wait at least tMRD.
DDR1 is in normal operation after 200 clock cycles starting with DLL reset.
2.1.7.2
DDR2 SDRAM Initialization
1. Apply voltage to the DDR2.1
2. Enable clock to the DDR2.
3. Wait until power and clock are stable.
4. Wait for 200 µs and thereafter send at least one NOP or deselect command.
5. Set CKE high.
6. Send NOP or deselect commands for 400 ns.
7. Send a precharge all command and thereafter wait at least tRP.
8. Send a load mode command to program EMR2 and thereafter wait at least tMRD.
9. Send a load mode command to program EMR3 and thereafter wait at least tMRD.
10. Send a load mode command to EMR to enable DLL and thereafter wait at least tMRD.
11. Send a load mode command to program MR with reset DLL and thereafter wait at least tMRD.
12. Send a precharge all command and thereafter wait at least tRP.
13. Send a refresh command and thereafter wait at least tRP.
14. Send a refresh command and thereafter wait at least tRP.1
15. Send a load mode command to program the mode register without DLL reset (A8=0) and thereafter
wait at least tMRD.
16. Wait until 200 clock cycles has passed after step 11 (DLL reset).
17. Send a load mode command to EMR to program OCD and thereafter wait at least tMRD.2
18. Send a load mode command to EMR to enable OCD default and thereafter wait at least tMRD.3
19. Send a load mode command to EMR to enable OCD exit and thereafter wait at least tMRD.3
DDR2 is in normal operation.
1. Perform at least two REFRESH commands.
2. Only required if OCD is used and step 18 and step 19 will not be executed.
3. If OCD is not used, then step 17 shall not be executed and steps 18 and 19 are required.
MPC5121e DRAM Controller, Rev. 2
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Freescale Semiconductor