Download AD820

CY7C63000/CY7C63001
CY7C63100/CY7C63101
CY7C63200/CY7C63201
PRELIMINARY
.
tCYC
tCH
CLOCK
tCL
Figure 8-1. Clock Timing
tf
tr
D+
90%
90%
10%
10%
D−
Figure 8-2. USB Data Signal Timing
9.0
Ordering Information
Ordering Code
EPROM
Size
Number
of GPIO
Package Type
Operating
Range
CY7C63000-PC
2KB
12
20-Pin (300-Mil) PDIP
Commercial
CY7C63000-SC
2KB
12
20-Pin (300-Mil) SOIC
Commercial
CY7C63001-PC
4KB
12
20-Pin (300-Mil) PDIP
Commercial
CY7C63001-SC
4KB
12
20-Pin (300-Mil) SOIC
Commercial
CY7C63001-WC
4KB
12
20-Pin (300-Mil) Windowed CerDIP
Commercial
CY7C63100-SC
2KB
16
24-Pin (300-Mil) SOIC
Commercial
CY7C63101-SC
4KB
16
24-Pin (300-Mil) SOIC
Commercial
CY7C63101-WC
4KB
16
24-Pin (300-Mil) Windowed CerDIP
Commercial
CY7C63200-PC
2KB
10
18-Pin (300-Mil) PDIP
Commercial
CY7C63201-PC
4KB
10
18-Pin (300-Mil) PDIP
Commercial
CY7C63201-WC
4KB
10
18-Pin (300-Mil) Windowed CerDIP
Commercial
Document #: 38-00557-D
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