Download System Generator for DSP User Guide

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Timing Analysis Compilation
You may click on the column headings to reorder the paths or elements according to delay,
slack, path name, or other column headings. Failing paths are highlighted in red/pink.
Name Unmunging and Displaying Low-Level Names
Part of the magic of the timing analyzer lies in its ability to perform the un-glorious task of
name unmunging, the task of automatically correlating System Generator components with
the low-level component names produced by the Xilinx implementation tools. The names
of these components often differ considerably. In fact, the logic blocks and wires that
appear in a System Generator diagram may have only a loose relation to the actual logic
that gets generated during the synthesis process. The System Generator timing analyzer
must correlate the names of logic elements and nets in the trace report to blocks and wires
in the System Generator diagram.
The timing analyzer cannot always perform this un-munging process. In the path shown in
the screen capture above, path elements #2 and #5 have a question mark displayed in the
name field. This means that the timing analyzer could not un-munge the name from the
trace report and correlate it to a System Generator block.
To see the actual names from the trace report, check the Display low-level names box. This
will show the trace report names. You may be able to correlate them to System Generator
elements by observation.
Cross-Probing
Highlighting a path in the Slow Paths view will highlight the blocks in the path in the
System Generator diagram. The path's source and destination blocks, as well as
combinational blocks through which the path passes, will be highlighted in red. The
diagram below shows how the model appears when the path that has Registerc as its
source and parity_reg as its destination is highlighted. The blocks xor_1b, xor_2a, and
xor_3a are also highlighted because they are part of the path.
System Generator for DSP
Release 10.1.3 September, 2008
www.xilinx.com
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