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Timer/Counter 2
Table 11−5. T2CON—Timer 2 Control (continued)
T2CON
Bit #
Name
0
CP/RL2
SFR C8h
Reset Value = 00h
Action or Interpretation
Capture/Reload Select.
TR2
RCLK
TCLK
CP/RL2
Mode
TF2 Overflow
0
x
x
x
Hold
1
0
0
0
16-bit Timer/Counter with auto-reload
Yes
1
0
0
1
16-bit Timer/Counter with capture
Yes
1
1
x
x
Baud Rate Generator
No
1
x
1
x
11.3.1 16-Bit Timer/Counter with Optional Capture
To select this mode, RCLK, TCLK, and CP/RL2 in T2CON must all be 0.
Control bit TR2 is active high and enables either an internal clock or an external
clock on pin P1.0/T2, according to the state of C/T2. Specifically, when C/T2
is 0, TH2:TL2 is a gated timer running at either fCLK /12 (default) or fCLK/4.
However, when C/T2 is 1, it is a gated event counter.
Figure 11−4. Timer/Counter 2—16-Bit with Capture
TF2
TH2
TL2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Timer 2
Interrupt
RCAP2L
RCAP2H
EXF2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Timer/Counter 2
16−Bit with Capture
Capture
Pin
T2EX
T2M is CKCON.5
EXEN2
fCLK/12 if T2M = 0
fCLK/4 if T2M = 1
1−to−0
Edge
Detection
Pin T2
0
C/T2
1
TR2
As TH2:TL2 overflows from FFFFh to 0000h, the interrupt flag (TF2) is set; this
must be cleared in software. If interrupt enables ET2 and EA (bits 5 and 7,
respectively, of IE at A8h) are both 1, the CPU jumps to the interrupt service
routine at 002Bh. Writing a ‘1’ to TF2 causes an interrupt, if it is enabled.
A negative-edge on pin P1.1/T2EX when control bit EXEN2 is 1 causes the
current value of TH2:TL2 to be copied into capture registers
RCAP2H:RCAP2L and sets the interrupt flag (EXF2). This is ORed with TF2
and may cause a Timer2 interrupt in a manner similar to TF2. EXF2 has to be
cleared in software and writing a ‘1’ to it causes an interrupt, if it is enabled.
Timers and Counters
11-9