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Glossary
port mode
A VHDL term that classifies the direction of the I/O
interface to a VHDL model. The most common port
modes for logic design are IN, OUT, INOUT, and
BUFFER.
product term
The result of two or more factors, combined in a Boolean
expression. Product terms are a common metric to
characterize the logic “capacity” of a PLD macrocell. A
PAL22V10, for example, supports 8 to 16 product terms.
programmable logic projects
A class of project types produced by the Programmable
Logic Wizard in Capture. Each project includes the
relevant library resources and project options optimized
for the target vendor.
project
A term used to collectively describe all files that
associated with a particular job. OrCAD Capture and
Simulate manage files and resources through the OrCAD
project file (.OPJ).
PROM
Programmable Read Only Memory. PROMs can be
developed with Express SPLD projects.
propagation delay
The time required for any signal transition to pass
between the ports of a logic element or the pins of a
device.
project manager
The window in which you specify files for your Simulate
project. The project manager is organized into folders,
each of which contains specific file types (VHDL, EDIF,
SDF, Session, and Other).
radix
The number base in which a signal value is displayed:
binary, octal, decimal, or hexadecimal.
RAM
Random Access Memory.
random access memory
An electronic storage element found on some FPGAs that
supports both read and write operations.
schematic design
A graphical representation of a circuit using a set of
electronic symbols, hierarchical blocks, and connections.
Typically used by system and programmable logic
designers to express a structural design description.
SDF
Standard Delay Format. Simulate uses SDF files to
perform timing simulation for post-route designs.
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