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Chapter 5 Logic synthesis and optimization
Interpreting optimization results
Note Static timing analysis and timing
optimization constraints are only available
if you have the Express Plus package.
As part of the optimization process, the synthesis engine
performs static timing analysis and produces some
statistic reports that relate the results of that analysis.
Static timing analysis allows for efficient evaluation of
timing hot spots in the design. The static timing analyzer
enables the synthesis engine to make a decision on area
and delay trade-off during synthesis and optimization.
Timing analysis traces the clocks to the registers in the
circuit, computes the delay along various instances in the
circuit, and helps to identify timing critical section of the
design. This type of analysis does not require generation
of circuit stimuli and requires less time than simulation.
However, timing analysis does not provide the functional
and dynamic simulation capabilities of a simulator.
Timing analysis is used in synthesis tools to guide timing
optimization and technology mapping. Critical paths in
the circuit are reported by checking the slack along the
path.
Slack is the difference between the required time and the
arrival time of a signal. A critical path has a negative slack
value. The path with the most negative slack is the most
critical path in the circuit. The longest path in the circuit is
not necessarily the most critical path, since a long path
may have a very late required time.
Arrival times are propagated along the circuit by adding
the delay across each gate to the arrival times of its inputs.
Delay across a gate not only depends on the delay through
the gate (the intrinsic delay) but also upon the loading of
the gate, the fanout connections, the interconnect load,
and the slew of the inputs of the gate. The delay
information can be expressed in a variety of local and
global constraints as described in Global timing constraints
on page 5-136 and Local synthesis and optimization constraints
on page 5-138.
The timing statistic reports for your design appear in the
session log window during the compilation. The
information in these reports is as follows:
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