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Download Comtech EF Data SDM-650B Specifications
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SDM-300L3 Satellite Modem Asynchronous Interface/AUPC RXD RT Revision 0 MN/SDM300L3.IOM RXD RXC BUF INT SAT INT PLL DDS EXT REF TERR MC EXT TT Note: PLL will be bypassed when the RX data rate is set to the TX data rate. This will disable the Asymmetrical Mode. Figure 12-2. Receive Section of the Asymmetrical Loop Timing Block Diagram Example: Master/Slave Clocking Setup: 1. Master site has a 10 MHz clock that is needed as the clock source. 2. Unequal data rates: 4.096 Mbps and 2.152 Mbps (numbers divisible by 8). Master Site Option: 1. Set Configuration/Modulator/Modem Reference to EXT 10 MHz. 2. Set Configuration/Interface/TX Clock Source to SCT (Internal). Note: The SCT clock is slaved off the 10 MHz input. The 10 MHz reference should be placed into CP3 of the modem. 3. Set Configuration/Interface/Buffer Clock to SCT (Internal). 12–3
