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OPB Serial Peripheral Interface
(SPI)
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Product Overview
Introduction
LogiCORE™ Facts
This document presents specifications for the VHDL implementation of the Motorola Serial Peripheral Interface (SPI)
in a Xilinx FPGA. The original specifications closely followed the Motorola M68HC11-Rev. 4.0 Reference Manual,
and this document emphasizes the M68HC-11 specifications. The design, however, was enhanced with a number
of exceptions and enhancements as described in this document. The default mode of operation has been changed to a
manual slave select operation (not included in the
M68HC11 specification).
The Serial Peripheral Interface (SPI) is a full-duplex, synchronous channel that supports a four-wire interface
(receive, transmit, clock, and slave select) between one
master and one slave. The original specifications followed
closely Motorola’s M68HC11-Rev. 4.0 Reference Manual.
There are differences from the 68HC11 specification that
should be reviewed when utilizing this SPI Assembly, see
the Specification Exceptions section of the datasheet.
The v1.00b specification has extended functionality, including a manual slave select mode, which lets you manually
control the slave select line directly by the data written to the
slave select register.
This allows transfers of an arbitrary number of bytes without
toggling the slave select line until all bytes are transferred.
In this mode, you must toggle the slave select by writing the
appropriate data to the slave select register. The manual
slave select mode is the default mode of operation.
This parameterized module permits additional slaves with
automatic generation of the required decoding of the individual slave select outputs by the master. Additional masters can be added as well; however, means to detect all
possible conflicts are not implemented with this interface
standard, but rather require the software to arbitrate bus
control in order to eliminate conflicts.
At this time only SPI slave devices are allowed off-chip. This
is an artifact of software master control arbitration which
can not be guaranteed if off-chip masters were allowed and
is due to issues with asynchronous external clocks as well.
Essentially any number of internal slave and master SPI
devices is allowed. The actual number is limited by the performance that is desired.
Core Specifics
Supported Device
Family
QPro™-R Virtex-II™,
QPro Virtex-II, Spartan-II™,
Spartan-IIE™, Spartan-3™,
Virtex™, Virtex-II™, Virtex-II
Pro™, Virtex-4™, Virtex-E
Version of Core
opb_spi
v1.00b
Resources Used
Min
Max
I/O
N/A
N/A
LUTs
N/A
N/A
FFs
N/A
N/A
Block RAMs
N/A
N/A
Provided with Core
Documentation
View this data sheet
Design File Formats
VHDL
Constraints File
None
Verification
N/A
Instantiation
Template
N/A
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
5.1i or later
Verification
N/A
Simulation
ModelSim SE/EE 5.6e or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
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