1
Download Processor IP Reference Guide
Transcript
0 OPB PCI Arbiter View this data sheet 0 0 Product Overview Introduction LogiCORE™ Facts The OPB PCI Arbiter provides arbitration among several PCI Master devices. Parametric selection determines the number of masters competing for PCI bus control. Both fixed and rotating arbitration schemes may be selected by programing a control register. Bus parking occurs in the case that no master requests PCI control. The particular master designated for parking is selected either with a programed register or by parametric selection. Register programming is accomplished through a slave interface to the OPB using the OPB_IPIF. An alternate use mode provides a PCI arbiter without an OPB interface. Achieved through appropriate parameter settings, this mode completely removes the program registers and the OPB_IPIF leaving open the outputs to the OPB and connecting inputs from the OPB to logic zero. Without an OPB interface the PCI arbiter operates with rotating arbitration and the park master is set directly by parameter selection. Core Specifics Supported Device Family Virtex-II Pro™, Virtex-II™, Virtex™, Virtex-E, Virtex-4™, QPro™-R Virtex-II, QPro Virtex-II, Spartan-II™, Spartan-IIE™, and Spartan-3™ Version opb_pci_arbiter Resources Used Min Max 4+2* C_NUM_PCI_M STRS 114 + 2 * C_NUM_PCI_ MSTRS LUTs 23 205 FFs 19 132 Block RAMs 0 0 I/O Features • v1.00a Provided with Core Variable number of PCI masters set by parameter Documentation View this data sheet • Fixed arbitration Design File Formats VHDL • Rotating arbitration Constraints File N/A • Control bit selection of arbitration scheme • Bus parking Verification N/A • Park master program register Instantiation Template N/A • Alternative park master set by parameter N/A • Control bit selection of park master Reference Designs & application notes • Removable processor interface, OPB_IPIF Additional Items None • Removable pipeline registers for PCI requests • Removable pipeline registers for PCI grants • OPB interface for register reads and writes Design Tool Requirements Xilinx Implementation Tools ISE 6.1.01i or later Verification N/A Simulation ModelSim SE/EE 5.6e or later Synthesis XST Support Provided by Xilinx, Inc. © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. Product Overview www.xilinx.com 1-800-255-7778 30
