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PLB Ethernet Media Access
Controller (PLB_EMAC) (v1.00a)
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Product Overview
Introduction
LogiCORE™ Facts
The Processor Logical Bus Ethernet 10/100 Mbs Media
Access Controller (PLB_EMAC) with interface to the Processor Local Bus (PLB) has been designed incorporating
the applicable features described in IEEE Std. 802.3 MII
interface specification. The IEEE Std. 802.3 MII interface
specification is referenced throughout this document and
should be used as the authoritative specification. Differences between the IEEE Std. 802.3 MII interface specification and the Xilinx EMAC implementation are highlighted
and explained in the Specifications Exceptions of the full
data sheet.
The PLB_EMAC Interface design is a soft intellectual property (IP) core designed for implementation in a Virtex-II Pro
FPGA. The PLB_EMAC design provides a 10 Megabits per
second (Mbps) and 100 Mbps (also known as Fast Ethernet) EMAC Interface. It includes many of the functions and
the flexibility found in dedicated Ethernet controller devices
currently on the market.
Features
The PLB EMAC is a soft IP core designed for Xilinx FPGAs
and contains the following features:
Core Specifics
Supported Device
Family
Virtex-II Pro™
Version of Core
plb_ethernet
Resources Used
Min
Max
Total Core I/Os
445
460
Core FPGA IOBs
13
19
LUTs
2000
37000
FFs
1500
2300
2
2
Block RAMs
Provided with Core
Documentation
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Design File Formats
NGC netlists, VHDL wrapper
Constraints File
UCF
•
64-bit PLB master and slave interfaces.
Verification
N/A
•
Memory mapped direct I/O interface to registers and
FIFOs as well as Simple DMA and Scatter/Gather DMA
capabilities for low processor and bus utilization.
Instantiation
Template
N/A
•
Media Independent Interface (MII) for connection to
external 10/100 Mbps PHY transceivers
Reference Designs
None
-
-
•
IEEE 802.3-compliant MII and management
control writes and reads with MII PHYs plus a
progreammable PHY reset signal
Supports auto-negotiable and non auto-negotiable
PHYs for 10BASE-T and 100BASE-TX/FX IEEE
802.3 compliant MII PHYs at full or half duplex
Independent internal TX and RX FIFOs ( 2K - 32 K) for
holding data for more than one packet. 2 K byte depth
is sufficient for normal 1518 maximum byte packets but
4 K byte depth provides better throughput.
v1.00a
Design Tool Requirements
Xilinx Implementation
Tools
ISE 6.1i or later
Verification
ModelSim PE 5.7b
Simulation
ModelSim PE 5.7b
Synthesis
Synplicity Pro 7.2
Support
Provided by Xilinx, Inc.
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you
may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
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