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OPB Central DMA Controller
(v1.00a)
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Product Overview
Introduction
LogiCORE™ Facts
The OPB Central DMA Controller provides simple Direct
Memory Access (DMA) services for peripherals and memory devices on the OPB bus. The controller moves a programmable quantity of data from a source address to a
destination address without processor intervention.
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•
Supported Device
Family
Version of Core
Features
•
Core Specifics
Provides a single physical channel of Direct Memory
Access between a source address and a destination
address.
Provides programmable registers for transfer length,
source address, destination address, and dataword
size.
Addresses may be set up as incrementing or
non-incrementing (for supporting keyhole type memory
devices)
•
Byte, halfword, and word data sizes supported.
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Provides fast internal data buffer to support OPB burst
transfers
Spartan-II™, Spartan-IIE™,
Spartan-3™, Virtex™, Virtex-II™,
Virtex-II Pro™, Virtex-E
opb_central_dma
v1.00a
Resources Used
Min
Max
Slices
180
208
LUTs
296
346
FFs
271
282
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0
Block RAMs
Provided with Core
Documentation
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Design File
Formats
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Constraints File
N/A
Verification
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Instantiation
Template
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Reference
Designs
N/A
Design Tool Requirements
Xilinx
Implementation
Tools
N/A
Verification
N/A
Simulation
N/A
Synthesis
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Support
Provided by Xilinx, Inc.
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trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you
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Product Overview
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