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PLB 1-Gigabit Ethernet Media Access Controller (MAC) with DMA (v1.00b)
GEMAC Endianess
Please note that the GEMAC is designed as a big endian device (bit 0 is the most significant bit and is shown on the left of
a group of bits).
The 8-bit GMII transmit and receive data interface to the external PHY is little endian (bit 7 is the most significant bit and
appears on the left of the bus). The MII management interface to the PHY is serial with the most significant bit of a field being
transmitted first.
Features
The GEMAC is a soft IP core designed for Xilinx FPGAs and contains the following features:
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64-bit PLB master and slave interfaces.
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Memory mapped direct I/O interface to registers and FIFOs as well as Simple DMA and Scatter/Gather DMA
capabilities for low processor and bus utilization..
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Optional Media Independent Interface Management (MIIM) for access to PHY transceiver registers
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GMII interface to external PHY devices
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Optional PCS function with Ten Bit Interface (TBI) to external PHY devices.
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Option PCS/PMA functions with SerDes interface to external transceiver devices for reduced signal count
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Independent internal 2 K, 4 K, 8 K, 16 K, or 32 K byte TX and RX FIFOs for holding data for more than one packet (2 K
byte depth is sufficient for normal 1518 maximum byte packets but 4 K byte depth provides better throughput. 16 K or
32 K byte depth is required for Jumbo frames up to 9 K bytes long)
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16 entry deep FIFOs for the Transmit Length, Receive Length, and Transmit Status registers to support multiple packet
operation
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Filtering of "bad" receive packets to reduce processor bus utilization
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Programmable PHY reset signal
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Auto pad and Frame Check Sequence (FCS) field insertion or pass through on transmit
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Auto pad and FCS field stripping or pass through on receive
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Processes transmission and reception of Pause frames for flow control
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Supports receive and transmit of longer VLAN type frames
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Programmable interframe gap
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Provides interrupts for many error and status conditions
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Optional support of jumbo frames up to 9K bytes in length
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No receive destination address validation. All properly formed packets are accepted.
Product Overview
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