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Appendix A Lessons
Processes Using QuickSim II
Principles of Top-Down Design
• Create a high level, functional model
o Technology independent
• Partition using functional blocks
• Use High-level Language Models
o VHDL (System-1076) or AutoLogic Blocks
• Simulate Functional Blocks
o Verify functionality
o models simulated directly in QuickSim II
• Synthesize for Technology -- Create gate-level
design from high-level language model
• Simulate Synthesized Design -- QuickSim II
o verify synthesized design functions
o estimate timing information
• Layout Design
o provides real timing and delay value
o timing saved in ASCII file or back annotations
• Simulate System Timing -- QuickSim II
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o
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A-2
merge back annotated timing
simulate to verify entire design
check all constraints
generate (save) test vectors
QuickSim II Advanced Training Workbook, 8.5_1
November 1995