1
Download The DatasheetArchive - Datasheet Search Engine
Transcript
Module SIPB 5135 W W C C W C /LINECA/EPIC/PCMCFI/POFD EF /LINECA/EPIC/PCMCFI/POFU 17 * transmit with rising edge, receive with falling edge of pcl /LINECA/EPIC/PCMCFI/PCSR 01 C C C C W C C C W C W C C W W C C C W C C C W C C W W C C C W C C C C C C C C C W W W C W W configuration of the cfi interface: * cfi mode 3, clock source: pcl/pfs * pfs evaluated with falling edge * prescaler = 1 /LINECA/EPIC/PCMCFI/CMD1 2C * fsc output: fc mode 6 * dc output: single rate * xmit rising, rec falling edge /LINECA/EPIC/PCMCFI/CMD2 C0 * cfi bit number is 64 /LINECA/EPIC/PCMCFI/CBNR 3F * pfs marks cfi ts0, bit7 * no shift between xmit and rec /LINECA/EPIC/PCMCFI/CTAR 02 /LINECA/EPIC/PCMCFI/CBSR 20 * subchannel position: 64kbps=bits7.0 32kbps=bits7.4 16kbps=bits7.6 /LINECA/EPIC/PCMCFI/CSCR 00 initialization of cm ctrl field: * cm reset mode /LINECA/EPIC/MARSCR/OMDR 00 * ff is copied to all positions of * the cm ctrl field /LINECA/EPIC/MARSCR/MADR FF /LINECA/EPIC/MARSCR/MACR 70 cfi configuration for sld: * cm init mode /LINECA/EPIC/MARSCR/OMDR 80 cfi time slots 2 and 3 of port 4 are programmed as downstream feature control and signaling channels, time slots 6 and 7 as upstream feature ctrl and signaling channels cfi ts 0-7 of port 4 represent thus sld port 4 (amc pin 10c) * ts 2 downstream: sig value ff is transmitted /LINECA/EPIC/MARSCR/MADR FF /LINECA/EPIC/MARSCR/MAAR 18 /LINECA/EPIC/MARSCR/MACR 7A * ts 3 downstream: /LINECA/EPIC/MARSCR/MADR 00 /LINECA/EPIC/MARSCR/MAAR 19 Semiconductor Group 372
