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B O A R D
H A R D W A R E
BTXD
BRXD
+3.3V
+3.3V
P5
U6
R75
10K
PWRRST
C2
+3.3V
0.1uF
11
9
1
12
2
4
5
6
C4
0.1uF
T1IN
R1OUT
T1OUT
R1IN
EN
FORCEON
FORCEOFF
INVALID
C1+
C1-
V+
V-
C2+
C2-
VCC
GND
13
8
TXD
RXD
1
3
5
7
9
16
10
2
4
6
8
10
3
7
15
14
C200
0.1uF
C205
0.1uF
C201
0.1uF
ICL3221
Figure 29 - MCU Serial Port
There are two signals attached to the MCU:
•
Transmit Data
•
Receive Data
TXD and RXD provide bi-directional transmission of transmit and receive data. No
hardware handshaking is supported.
3.2 CPLD
The Xilinx XC95288XV (U5) CPLD is needed to handle the counters and state
machines associated with the high-speed interface to the SmartMedia card.
Approximately 90% of the resources of this device are utilized, so 10% are available to
the user. The Verilog source code for the CPLD (CPLD.V) is provided on the CDROM.
The CPLD performs the following functions:
•
Interface to the Micro Controller
− Data Bus: UPAD[0..7]
− Control Signals: UP_RDn, UP_WRn, UP_ALE
− Clock: MCU_CLK
•
Interface to the SmartMedia
− Data Bus: SM_D[0..7]
− Control Signals: SM_REn, SM_WEn, SM_ALE, SM_CLE, SM_CEn,
SM_RDYBUSYn
•
FPGA Configuration, Serial/SelectMap
− Data Bus: FPGA_D[0..7]
ET6000K10S User Guide
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