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Download GRLIB IP Core User`s Manual
Transcript
COBHAM GAISLER 779 GRIP When using dynamic filtering, the core will ignore all pulses shorter than the system clock period multiplied with the value of the FILT field in the core’s Dynamic Filter register and may also ignore pulses that are shorter than 2 * FILT * (system clock period) - 1. 64.3 Registers The core is programmed through registers mapped into APB address space. Table 1013.I2C-master registers APB address offset Register 0x00 Clock prescale register 0x04 Control register 0x08 Transmit register* 0x08 Receive register** 0x0C Command register* 0x0C Status register** 0x10 Dynamic filter register*** * Write only ** Read only *** Only available on some implementations Table 1014. I2C-master Clock prescale register 31 16 15 7 6 5 RESERVED 4 3 2 1 0 Clock prescale 31 : 16 RESERVED 15:0 Clock prescale - Value is used to prescale the SCL clock line. Do not change the value of this register unless the EN field of the control register is set to ‘0’. The minimum recommended value of this register is 0x0003. Lower values may cause the master to violate I2C timing requirements due to synchronization issues. Table 1015. I2C-master control register 31 8 RESERVED 7 6 EN IEN 5 0 RESERVED 31 : 8 RESERVED 7 Enable (EN) - Enable I2C core. The core is enabled when this bit is set to ‘1’. 6 Interrupt enable (IEN) - When this bit is set to ‘1’ the core will generate interrupts upon transfer completion. 5:0 RESERVED Table 1016. I2C-master transmit register 31 8 RESERVED 7 1 TDATA 0 RW 31 : 8 RESERVED 7:1 Transmit data (TDATA) - Most significant bits of next byte to transmit via I2C 0 Read/Write (RW) - In a data transfer this is the data’s least significant bit. In a slave address transfer this is the RW bit. ‘1’ reads from the slave and ‘0’ writes to the slave.
