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COBHAM GAISLER 942 GRIP 74.13.3 Memory configuration register 3 (MCFG3) MCFG3 is contains the reload value for the SDRAM refresh counter. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RESERVED 9 8 SDRAM REFRESH RELOAD VALUE 31: 27 RESERVED 26: 12 SDRAM refresh counter reload value (SDRAM REFRESH RELOAD VALUE) 11: 0 RESERVED 7 6 5 4 3 2 3 2 1 0 RESERVED The period between each AUTO-REFRESH command is calculated as follows: tREFRESH = ((reload value) + 1) / SYSCLK Table 1182. MCFG4 Power-Saving configuration register 31 30 29 28 ME CE EM 24 23 Reserved 20 19 18 tXSR res 16 15 PMODE 7 Reserved 6 5 DS 4 TCSR 0 PASR 31 Mobile SDRAM functionality enabled. ‘1’ = Enabled (support for Mobile SDRAM), ‘0’ = disabled (support for standard SDRAM) 30 Clock enable (CE). This value is driven on the CKE inputs of the SDRAM. Should be set to ‘1’ for correct operation. This register bit is read only when Power-Saving mode is other then none. 29 EMR. When set, the LOAD-COMMAND-REGISTER command issued by the SDRAM command field in MCFG2 will be interpret as a LOAD-EXTENDED-COMMAND-REGISTER command. 28: 24 Reserved 23: 20 SDRAM tXSR timing. tXSR will be equal to field-value system clocks. (Read only when Mobile SDR support is disabled). 19 Reserved 18: 16 Power-Saving mode (Read only when Mobile SDR support is disabled). “000”: none “001”: Power-Down (PD) “010”: Self-Refresh (SR) “101”: Deep Power-Down (DPD) 15: 7 Reserved 6: 5 Selectable output drive strength (Read only when Mobile SDR support is disabled). “00”: Full “01”: One-half “10”: One-quarter “11”: Three-quarter 4: 3 Reserved for Temperature-Compensated Self Refresh (Read only when Mobile SDR support is disabled). “00”: 70ªC “01”: 45ªC “10”: 15ªC “11”: 85ªC 2: 0 Partial Array Self Refresh (Read only when Mobile SDR support is disabled). “000”: Full array (Banks 0, 1, 2 and 3) “001”: Half array (Banks 0 and 1) “010”: Quarter array (Bank 0) “101”: One-eighth array (Bank 0 with row MSB = 0) “110”: One-sixteenth array (Bank 0 with row MSB = 00)
