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Download CubeSuite+ V1.00.00 Integrated Development Environment User`s
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CubeSuite+ Ver.1.00.00 CHAPTER 4 ASSEMBLY LANGUAGE SPECIFICATIONS As shown in above figure, when an STSR instruction is placed immediately after an LDSR instruction that uses the operand EIPC or FEPC, and that STSR instruction uses the LDSR instruction execution result, the interlock function causes a data wait time to occur, and the execution speed is lowered. This drop in execution speed can be avoided by placing STSR instructions that reference the execution result of the preceding LDSR instruction at least 3 instructions after the LDSR instruction. (e) Cautions when creating programs When creating programs, pipeline disorder can be avoided and instruction execution speed can be raised by observing the following cautions. - Place instructions that use the execution result of load instructions (LD, SLD) at least 2 instructions after the load instruction. - Place instructions that use the execution result of multiply instructions (MULH, MULHI) at least 2 instructions after the multiply instruction. - If using the STSR instruction to read the setting results written to the EIPC or FEPC registers with the LDSR instruction, place the STSR instruction at least 3 instructions after the LDSR instruction. - For the first branch destination instruction, use a 2-byte instruction, or a 4-byte instruction placed at a word boundary. (5) Additional Items Related to Pipeline (a) Harvard architecture The V850ES uses Harvard architecture to operate an instruction fetch path from internal ROM and a memory access path to internal RAM independently. This eliminates path arbitration conflicts between the IF and MEM stages and allows orderly pipeline operation. <1> V850ES (Harvard architecture) The MEM stage of instruction 1 and the IF stage of instruction 4, as well as the MEM stage of instruction 2 and the IF stage of instruction 5 can be executed simultaneously with an orderly pipeline operation. instruction 1 instruction 2 instruction 3 instruction 4 instruction 5 R20UT0553EJ0100 Rev.1.00 Apr 01, 2011 <1> <2> <3> <4> <5> <6> IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM <7> <8> <9> WB Page 577 of 943
