Download MELSEC-L CPU Module User`s Manual (Hardware Design

Number
Name
Meaning
Set by
(When Set)
Explanation
Correspo
nding
ACPU
D9
SD240
Correspo
nding
CPU
Base mode
0: Automatic
mode
1: Detail mode
This register stores the base mode.
QCPU
Extension stage
number
0: Main base only
1 to 7: Number of
extension base
units
This register stores the maximum number of extension base
units installed.
QCPU
Number of
extension blocks
0: Main only
1 to 3: Number of
extension blocks
This register stores the maximum number of connected
extension blocks.
LCPU*9
A/Q base
differentiation
Base type
differentiation
0: QA**B is
installed (A
mode)
1: Q**B is
installed (Q
mode)
SD241
b7
b2 b1 b0
Fixed to 0
to
Qn(H)
QnPH
QnPRH
Main base unit
1st extension base
2nd extension base
to
7th extension base
Fixed to 0
when the
base is not
installed.
S (Initial)
Installed Q base
presence/
absence
SD242
Base type
differentiation
0: Base not
installed
1: Q**B is
installed
b4
New
b2 b1 b0
Fixed to 0
to
Main base unit
1st extension base
2nd extension base
Q00J/Q00/
Q01
to
4th extension base
A/Q base
differentiation
370
Base type
differentiation
0: QA1S**B,
QA1S6ADP+A1S
*B, QA**B, and
QA6ADP+ A**B
are installed /
Base not
installed
1: Q**B is
installed
b7
Fixed to 0
b2 b1 b0
to
Main base unit
1st extension base
2nd extension base
to
7th extension base
Fixed to 0
when the
base is not
installed.
• For the Q00UJCPU, the bits for the third to seventh extension
bases are fixed to "0".
• For the Q00UCPU, Q01UCPU, and Q02UCPU, the bits for
the fifth to seventh extension bases are fixed to "0".
QnU