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Download Overview Programming Model Cache and Bus Interface Unit
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Table 8-3. Burst Ordering For Starting Address: Data Transfer A[27–28] = 00 A[27–28] = 01 A[27–28] = 10 A[27–28] = 11 First data beat DW0 DW1 DW2 DW3 Second data beat DW1 DW2 DW3 DW0 Third data beat DW2 DW3 DW0 DW1 Fourth data beat DW3 DW0 DW1 DW2 Note: A[29–31] are always 0b000 for burst transfers by the 604e. 8.3.2.4 Effect of Alignment in Data Transfers Table 8-4 lists the aligned transfers that can occur on the 604e bus. These are transfers in which the data is aligned to an address that is an integer multiple of the size of the data. For example, Table 8-4 shows that one-byte data is always aligned; however, for a four-byte word to be aligned, it must be oriented on an address that is a multiple of four. Table 8-4. Aligned Data Transfers Data Bus Byte Lane(s) Transfer Size Byte Half word Word Double word TSIZ0 TSIZ1 TSIZ2 A[29–31] 0 1 2 3 4 5 6 7 0 0 1 000 √ — — — — — — — 0 0 1 001 — √ — — — — — — 0 0 1 010 — — √ — — — — — 0 0 1 011 — — — √ — — — — 0 0 1 100 — — — — √ — — — 0 0 1 101 — — — — — √ — — 0 0 1 110 — — — — — — √ — 0 0 1 111 — — — — — — — √ 0 1 0 000 √ √ — — — — — — 0 1 0 010 — — √ √ — — — — 0 1 0 100 — — — — √ √ — — 0 1 0 110 — — — — — — √ √ 1 0 0 000 √ √ √ √ — — — — 1 0 0 100 — — — — √ √ √ √ 0 0 0 000 √ √ √ √ √ √ √ √ Chapter 8. System Interface Operation 8-15
