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Chapter 9: General Purpose Registers
Transmitter Termination Control Register
The Transmitter Termination Control Register sets the transmit line return loss resistor values
for the QuadFALC Line Interface Units. The bits in the register control a set of analog switches
that connect the termination resistors in and out of the transmitter circuit. The control function
groups port 0 and port 1 into a set of termination choices and ports 2 and 3 into another set of
termination choices. The tables below outline the various configuration possibilities.
See Table 9-38 and Table 9-39.
Table 9-38: Transmitter Termination Control Register Bit Fields
MPC8260 Bit
0(MSB)
1
2
3
4
5
6
7(LSB)
Buffered Bus Bit
7(MSB)
6
5
4
3
2
1
0(LSB)
RSVD
RSVD
23tterm1
23tterm0
RSVD
RSVD
01tterm1
01tterm0
0
0
0
0
0
0
0
0
RO
RO
R/W
R/W
RO
RO
R/W
R/W
Field
Reset Value
R/W
Address
Base+5FH
Table 9-39: Transmitter Termination Control Register Bit Field Definition
Bits
Name
Description
0-1
01tterm0,
01tterm1
01tterm0,
01tterm1
Termination
Value
00
For 100 Ohm
T1, 110 Ohm
J1, 120 Ohm
E1 return loss
11
75 Ohm E1
return loss
2-3
RSVD
Reserved, this bit is always set to 0.
4-5
23tterm0,
23tterm1
23tterm0,
23tterm1
Termination
Value
00
For 100 Ohm
T1, 110 Ohm
J1, 120 Ohm
E1 return loss
01
75 Ohm E1
return loss
6-7
102
Set these bits to match the T1, J1, E1 interface
being used.
RSVD
Set these bits to match the T1, J1, E1 interface
being used.
Reserved, this bit is always set to 1.