Download PCI384

Quad Framers and LIUs Physical Configuration
Local TDM Receive Data Pin Configuration
Each of the received data streams is actually sourced from an internal elastic data store device
which rate compensates between the trunk input rate and the local TDM stream. Each of the
four elastic stores multiplexes its receive data onto the RDO1 output pin for termination in the
connection memory of the H.100 TDM switch. The RDO1 data stream is synchronized to the
local TDM timing via the H.100 switch's local clock and frame sync. The local streams are all
setup to use an 8.192 Mb/s transfer rate regardless of the line side operating rate. Refer to the
datasheet for the proper control registers and their settings to achieve the multiplexed
configuration.
Local TDM Receive System Clock Pin Configuration
The framer has an elastic data store on the receive data output. The elastic store is used to
compensate between the receiver trunk line rate and the local TDM data rate. In the
multiplexed data mode, the clock input pin SCLKR1 is used to supply the elastic data stores
with a clock that is synchronized to the local TDM. The clock has a fixed input frequency of
8.192 MHz. The SIC2.SSC2 bits are used to scale the clocks input so that each of the four
elastic stores can comply to the 8 Mb/s data rate. Refer to the datasheet for the proper control
registers and their settings.
Local TDM Receive Frame Pulse Input Pin Configuration
The framers' receive data output is connected to the local TDM bus. The data output stream is
sourced from the respective framer's elastic data store. In order to properly synchronize the
operation of elastic data store to the local system timing a Frame Pulse is required. The H.100
switch sources the 8 KHz frame pulse. The signal is input to each of the framers on the
Receive Multifunction Port A pin 1. This function is called the SYPR or Synchronous Pulse
receive mode for the Receive Multifunction pin 1 on each port. Refer to the datasheet for the
proper control registers and their settings.
Receive Channel Associated Signaling
Each of the four framers' Channel Associated Signaling (CAS) is multiplexed onto the RPB1
(programmed as RSIG) pin for connection to the local TDM bus. The CAS is terminated in the
H.100 connection memory and from there it can be routed out onto the H.100 bus or terminated
in the MPC8260. The CAS is transmitted the local TDM bus at the 8.192 Mb/s transfer rate.
Refer to the datasheet for the proper control registers and their settings to achieve the
multiplexed configuration on RPBI at the 8.192 MHz rate.
Local TDM Transmit Data Pin Configuration
The transmit data source for all four framers is the H.100 switch’s connection memory. Data for
each framer is multiplexed onto one TDM stream by the switch and delivered to the framer at
an 8.192 Mb/s rate. The QuadFALC receives the multiplexed data stream on the XDI1 pin. The
XDI1 pin is synchronized to the board TDM streams by the H.100's 8.192 MHz clock and
8 KHz frame pulse.
79