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Chapter
6
TDM Clocking
Overview
The TDM clock distribution is centralized about the Zarlink MT90866 H.100 TDM switch located
on the mezzanine I/O board. This device generates all of the local TDM Frame Pulses and data
clocks. It uses a variety of clock sources to lockup its internal digital phase locked loop (DPLL)
to a system reference. This ability ensures that the data transferred on the board stays in
synchronization with the system and no timing slips occur.
See Figure 6-1, “TDM Clock Tree,” on page 63, for a visual representation of the circuit.
Key topics in this chapter include:
•
“H.100 DPLL,” on page 60
•
“Internal Reference Clock Sources,” on page 61
•
“Internal Reference Monitors,” on page 61
•
“CT Clock and Frame Monitor Circuits,” on page 61
•
“External Reference Clock Sources,” on page 61
•
“External Reference Clock Source Monitor,” on page 62
•
“H.100 Clock Operating Modes,” on page 62
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