Download USP-2 Hardware Manual

USP-2 Hardware Manual
4.5.1.1
PIO Operation
A processor which wishes to access the SBus makes a UPA request which is forwarded to the U2S. The U2S
processes the request, and if it is intended for the SBus, routes it down to that bus. Write operations are
buffered. Errors are reported asynchronously. Refer to Chapter 9 of the Programmer’s Guide, Error Handling,
for more details on the error behavior.
Note — Hardware detection of synchronization between DVMA writes and PIO reads to the SBus is not
provided.
4.5.1.2
DVMA Operation
All DMA transactions from SBus are actually DVMA transactions. This means that a virtual address is put on
the SBus, and the U2S chip performs translation of that virtual address into a physical address recognized by
the system. Translation is performed by the IOMMU. Bypass is provided for when translation is not desired.
4.5.1.3
Interrupt Dispatching
All interrupts on the UPA are performed as transactions (packets). The U2S works in conjunction with the
RIC ASIC to translate level sensitive interrupts into packets which are delivered to the processor. Registers
are present to control the mapping between the physical interrupt wire, and the corresponding code delivered
in the interrupt packet. Registers also control the target of the interrupt. Interrupt transactions which go out on
the UPA will never pass DVMA transactions which occurred prior to the interrupt. DVMA transactions may
pass an interrupt.
4.5.1.4
UPA Interface
The U2S implements a 72 bit UPA interface.
4.5.1.5
ECC Checking / Generation
All packets to or from the UPA have ECC. The U2S logic performs ECC generation and checking.
4.5.1.6
SBus Interface
One of the major functions of the U2S is to bridge the UPA and SBus. It implements an IEEE P1496
compliant SBus interface.
4.5.1.7
Streaming Buffer
Streaming Buffers perform read-ahead / write-behind transfers to speed up sequential I/O activity. The
transfers act to buffer data on the way to or from memory.
4-10
Themis Computer