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Download ADSP-2136x SHARC® Processor Hardware Reference
Transcript
Registers Reference Table A-45. DITCTL Register Bit Descriptions Bit Name Description 0 DIT_EN Transmitter Enable. Enables the transmitter and resets the control registers to their defaults. 0 = Transmitter disabled 1 = Transmitter enabled 1 DIT_MUTE Mute. Mutes the serial data output. 3–2 DIT_FREQ Frequency Multiplier. Sets the over sampling ratio to the following: 00 = 256 x frame sync 01 = 384 x frame sync 10 = 512 x frame sync 11 = 768 x frame sync 4 DIT_SCDF Enable Single-channel, Double-frequency Mode. 0 = Normal mode 1 = SCDF mode 5 DIT_SCDF_LR Select Single-channel, Double-frequency Mode. 0 = Left channel 1 = Right channel 8–6 DIT_SMODEIN Serial Data Input Format. Selects the input format as follows: 000 = Left-justified 001 = I2S 010 = reserved 011 = reserved 100 = Right-justified, 24-bits 101 = Right-justified, 20-bits 110 = Right-justified, 18-bits 111 = Right-justified, 16-bits 9 DIT_AUTO Automatically Generate Block Start. Automatically generate block start. When enabled, the transmitter is in standalone mode where it inserts block start, channel status, and validity bits on its own. 0 = Manually start block transfer according to input stream status bits 1 = Automatically start block transfer. 10 DIT_VALIDL Validity Bit A. Use with channel status buffer. 11 DIT_VALIDR Validity Bit B. Use with channel status buffer. ADSP-2136x SHARC Processor Hardware Reference for the ADSP-21362/3/4/5/6 Processors A-133
