Download ADSP-2136x SHARC® Processor Hardware Reference

Parallel Port
• For core-driven transfers over the parallel port, the IIPP, IMPP,
ICPP, and ECPP registers are not used. Only the EIPP and EMPP registers need to be initialized before accessing the TXPP or RXPP buffers.
• All core writes (including to the PPCTL register) wait during chain
pointer loading. However, any register can be read during chain
pointer loading.
Known-Duration Accesses
Of the four core-driven data transfer methods, known duration accesses
are the most efficient because they allow the core to execute code while the
transfer to/from the RXPP or TXPP occurs on the external bus. For example,
after the core reads the PPTX register, it takes some number N core cycles
for the parallel port to shift out that data to the memory. During that
time, the core can go on doing other tasks. After N core cycles have
passed, the parallel port may be disabled and the external address register
updated for another access.
To determine the duration for each access, the designer simply adds the
number of data cycles and the duration of each (measured in CCLK cycles)
along with the number of ALE cycles (which are fixed at 3 PCLK cycles).
This duration is deterministic and based on two settings in the PPCTL register—parallel port data cycle duration (PPDUR) and bus hold cycle enable
(PPBHC).
Please refer to “Parallel Port Operation” on page 3-5 for further explanation of the parallel port bus cycles, but in summary, programs can use the
following values.
• Each PCLK is two CCLK cycles.
• Each ALE cycle is fixed at three PCLK cycles, regardless of the PPDUR
or PPBHC settings.
• Each data cycle is the setting in the PPDUR register (+1 if PPBHC =1)
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
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