Download TSC695F 32-bit Sparc Processor

– Floating-point compare operations: when one or more of the operands are
NaN.
Division-by-zero (%fsr’s cexc field = 00010b) –
If the divisor is zero and the dividend is a
finite nonzero number, then the division by zero exception shall be signaled. The result, when
no trap occurs, shall be a correctly signed ∞.
Overflow (%fsr’s cexc field = 0100xb) – The exceeded in magnitude by what would have
been the rounded floating-point result were the exponent range unbounded. The
result, when no trap occurs, shall be determined by the rounding mode and the sign
of the intermediate result as follows:
– Round to nearest carries all overflows to ∞ with the sign of the intermediate result,
– Round toward 0 carries all overflows to the format’s largest finite number with
the sign of the intermediate result,
– Round toward –∞ carries positive overflows to the format’s largest positive finite
number, and carries negative overflows to –∞,
– Round toward + ∞ carries negative overflows to the format’s most negative finite
number, and carries positive overflows to +∞.
Underflow (%fsr’s cexc field = 0010xb) – The TSC695F’s FPU asserts an underflow
exception when the rounded result is inexact and would be smaller in magnitude than
the smallest normalized number in the specified format.
Inexact (%fsr’s cexc field = 0xx01b) – The inexact exception is generated whenever there
is a loss of accuracy (or significance) in the result. The TSC695F’s FPU computes
results to higher precision than the number of fraction bits in the format. If any of the
fraction bits to the right of the LSB was one prior to rounding, the inexact exception is
signaled.
Unfinished FPop
– The TSC695F’s FPU never asserts this exception since all implemented
instructions are executed within hardware.
– Data access exception
A data access exception trap is generated if a parity error, uncorrectable EDAC
error, access violation, bus timeout or system bus error is detected (MEXC signal is
asserted) during the data cycle of any instruction that moves data to or from
memory.
– Tag overflow
This trap occurs if execution of a TADDccTV or TSUBccTV instruction causes the
overflow bit of the integer condition codes to be set. See the instruction definitions of
TADDccTV and TSUBccTV for details.
– Trap instructions
This trap occurs when a Ticc instruction is executed and the trap conditions are met.
There are 128 programmable trap types available within the trap instruction trap.
See SPARC V7.0 Instruction Set, Ticc instruction for details.
3.6.7.2
Interrupts or
Asynchronous
Traps
TSC695F User Manual
The TSC695F handles 15 asynchronous traps.
It is possible to mask each individual interrupt (except for interrupt 15 – watch-dog) by
setting the corresponding bit in the Interrupt Mask Register (INTMKR). The Interrupt
Pending Register (INTPDR) reflects the pending interrupts. It is possible to clear pending interrupts by setting the corresponding bit in the Interrupt Clear Register (INTCLR).
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