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Download SPEAr320 address map and registers
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SPEAr320 31.2.5 Reconfigurable array subsystem (RAS) RAS select register Table 635. RAS select register (0xB300_000C) Bits Default value Description [31:15] 17’h1111 Reserved 1’h1 FrRDA Alternate function enable This bit enables the alternate function on the PL_GPIO_0 and PL_GPIO_1 pins. ‘1’- IrDA_RX and IrDA_TX alternate functions enabled ‘0’ - RAS function enabled 1’h1 I2C Alternate function enable This bit enables the alternate function on the PL_GPIO_4 and PL_GPIO_5 pins. ‘1’ - I2C0_SCL and I2C0_SDA alternate functions enabled ‘0’ - RAS function enabled 1’h1 SSP0 enhanced (CS (2-3-4)) Alternate function enable This bit enables the alternate function on the PL_GPIO_34, PL_GPIO_35 and PL_GPIO_36 pins. ‘1’ - SSP0_CS4, SSP0_CS3 and SSP0_CS2 alternate functions enabled ‘0’ - RAS function enabled 1’h1 SSP0 Basic (no CS (2-3-4)) Alternate function enable This bit enables the alternate function on the PL_GPIO_6, PL_GPIO_7, PL_GPIO_8 and PL_GPIO_9 pins. ‘1’ -SSP0_MOSI, SSP0_CLK, SSP0_SS0 and SSP0_MISO alternate functions enabled ‘0’ - RAS function enabled 1’h1 MAC Ethernet (MII0) Alternate function enable This bit enables the alternate function on the PL_GPIO_10 to PL_GPIO_27 pins. ‘1’- MII0 alternate functions enabled ‘0’ - RAS function enabled 1’h1 basGPIO0 alternate function enable This bit enable the basGPIO0 alternate function on the PL_GPIO28 pin ‘1’- basGPIO0 alternate function enabled ‘0’ - RAS function enabled 1’h1 basGPIO1 alternate function enable This bit enable the basGPIO1 alternate function on the PL_GPIO29 pin ‘1’- basGPIO1 alternate function enabled ‘0’ - RAS function enabled 1’h1 basGPIO2 alternate function enable This bit enable the basGPIO2 alternate function on the PL_GPIO30 pin ‘1’- basGPIO2 alternate function enabled ‘0’ - RAS function enabled [14] [13] [12] [11] [10] [09] [08] [07] Doc ID 022180 Rev 1 495/533
