Download SPEAr320 address map and registers

SPEAr320
Security co-processor (C3)
Bits 8 to 2 - Step Count (SCNT)
These 7 bits represent the hash round in progress.
Bit 1 - Last Word Asserted (LAST)
This bit indicates if the whole message has been passed to the core.
Bit 0 - Reserved
This bit is reserved and should be written zero.
Hash Status Registers (UHH_HX0 - UHH_HX7)
The Hash Status Registers contain the current partial value of the digest.
Hash Working Registers (UHH_X0 - UHH_X7)
The Hash Working Registers contain a temporary value used for the computation of the
digest.
Message Scheduler Registers (UHH_WX0 - UHH_WX15)
The Message Scheduler Registers contain the unrolled message.
Current Hash Constant Register (UHH_UHR)
The Current Hash Register contains the current result of the internal Hash function.
Bit Count Registers (UHH_BCLO - UHH_BCHI)
The Bit Count Registers contain the cumulated length of the processed message.
HMAC Key Digest Registers (UHH_RK0 - UHH_RK7)
The HMAC Key Digest Registers contain the computed digest of the HMAC key.
HMAC Working Registers (UHH_RH0 - UHH_RH7)
The HMAC Working Registers contain a temporary value used for the computation of the
HMAC.
Channel ID (UHH_CH_ID)
The Channel ID register contains the Identifier of this version of the UHH Channel. The
Channel ID for this version of the UHH channel is 0x0000_4002.
Doc ID 022180 Rev 1
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