Download HUNT ENGINEERING HERON

TABLE OF CONTENTS
INTRODUCTION.......................................................................................................... 6
PHYSICAL LOCATION OF ITEMS ON THE HERON-IO5.................................. 8
GETTING STARTED ................................................................................................... 9
STANDARD INTELLECTUAL PROPERTY (IP) ............................................................................................. 9
MODULE FEATURES ............................................................................................... 10
SERIAL CONFIGURATION OF THE USER FPGA ....................................................................................... 10
BOOT ROM........................................................................................................................................... 10
CLOCKING OF THE FPGA ...................................................................................................................... 11
HERON FIFOS .................................................................................................................................... 12
ANALOG I/O .......................................................................................................................................... 13
A/D clocking .................................................................................................................................... 13
D/A clocking .................................................................................................................................... 14
DIGITAL I/O........................................................................................................................................... 14
MODULE AND CARRIER ID .................................................................................................................... 15
GENERAL PURPOSE LEDS ..................................................................................................................... 15
DONE LEDS .......................................................................................................................................... 15
GETTING STARTED ON YOUR FPGA DESIGN ................................................. 16
WORKING THROUGH EXAMPLE 1........................................................................................................... 17
Preparing ISE .................................................................................................................................. 17
Copying the examples from the HUNT ENGINEERING CD........................................................... 18
Opening the Example1 Project........................................................................................................ 18
The Project's functional parameters................................................................................................ 18
Setting up the Configuration Package............................................................................................. 19
User Timing Constraints.................................................................................................................. 22
Creating the Bitstream for Example1 .............................................................................................. 24
Simulating the complete design ....................................................................................................... 25
MAKING YOUR OWN FPGA DESIGN................................................................... 26
USER_AP INTERFACE ............................................................................................................................ 26
HARDWARE INTERFACE LAYER ............................................................................................................. 31
IMPORTANT!.......................................................................................................................................... 33
OTHER EXAMPLES ................................................................................................................................. 33
HOW TO MAKE A NEW DESIGN ............................................................................................................. 34
Inserting your own Logic................................................................................................................. 34
Top-level fine tuning (using other special IO pins) ......................................................................... 34
User Timing Constraints.................................................................................................................. 35
HINTS FOR FPGA DESIGNS .................................................................................................................... 35
Use of Clocks ................................................................................................................................... 36
Possible Sources of Clocks .............................................................................................................. 36
Flow Control.................................................................................................................................... 37
Pipeline Length or “latency” .......................................................................................................... 37
DIGITAL I/O FROM THE FPGA............................................................................................................... 37
DSP WITH YOUR FPGA......................................................................................................................... 38
CHIPSCOPE ............................................................................................................................................ 38
SOFTWARE................................................................................................................. 40
FPGA DEVELOPMENT TOOL.................................................................................................................. 40
DESIGN FILES FOR THE FPGA ............................................................................................................... 40
GENERATING DESIGN FILES................................................................................................................... 41
Files for HERON Utility (*.RBT)..................................................................................................... 41
Files for direct JTAG programming (*.bit) ..................................................................................... 42
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HUNT ENGINEERING HERON-IO5V USER MANUAL