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Simulator Overview
A/D Converter (Limited)
All the registers, timing function and interrupt generation are implemented. The
simulator, however, does not load any meaningful value into the A/D result registers
(ADRES) at the end of a conversion.To load meaningful data, use an injection file (see
Section 18.2.5 “Register Injection”). A read of the A/D registers will load this data
into the registers.
Note:
If you have trouble with I/O pins on processors that have A/D, make certain
that the ADCON registers are configuring those pins for digital I/O rather
than for analog input. For most processors, these default to analog inputs
and the associated pins cannot be used for I/O until the ADCON registers
are set properly.
Because simulation is to the register level, and not the pin level, bit/pin names will be
read as ‘0’, as required for analog, although injected stimulus may have actually
changed the value to ‘1’.
USART
USART functionality is supported. For more information, see Section 17.7 “Using a
USART/UART”.
EEPROM Data Memory
The EEPROM data memory is fully simulated. The registers and the read/write cycles
are fully implemented. The write cycle time is approximated to 10 ms (to nearest
instruction cycle multiple).
The simulator simulates the functions of WRERR and WREN control bits in the
EECON1 register.
16.3.6
24-Bit Core Device Simulation – PIC24 MCUs / dsPIC DSCs
The following topics discuss the PIC24/dsPIC DSC device features modeled in the simulator.
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Exceptions (Traps/Interrupts)
System Integration Block
Memory
Peripherals
16.3.6.1
EXCEPTIONS (TRAPS/INTERRUPTS)
The simulator supports all core and peripheral traps and interrupts, even if the
peripheral is currently not supported.
The dsPIC DSC core features a vectored exception processing structure for up to 8
traps and 54 interrupts or 62 total independent vectors. Each interrupt is prioritized,
based on a user-assigned priority between 1 and 7 (1 being the lowest priority and 7
being the highest). If a conflict occurs (two interrupts at the same priority), interrupt service will be based on a predetermined 'natural order' which is hardware-based.
© 2006 Microchip Technology Inc.
DS51519B-page 217