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DesignWare IP Family
DW_asymfifoctl_s2_sf
Asymmetric Synchronous (Dual-Clock) FIFO Controller with Static Flags
Table 2: Parameter Description (Continued)
Values
1 to 3
pop_sync
1 to 3
rst_mode
0 or 1
byte_order
0 or 1
Default: 0
Description
Push flag synchronization mode
1 = single register synchronization from pop pointer,
2 = double register,
3 = triple register)
Pop flag synchronization mode
1 = single register synchronization from push pointer,
2 = double register,
3 = triple register)
Reset mode
0 = asynchronous reset,
1 = synchronous reset)
Order of bytes or subword within a word
0 = first byte is in most significant bits position;
1 = first byte is in the least significant bits position).
DWL Sythesizable IP
Parameter
push_sync
Table 3: Synthesis Implementationsa
Implementation Name
rpl
cl2
Function
Ripple carry synthesis model
Full carry look-ahead model
License Feature Required
DesignWare
DesignWare
a. During synthesis, Design Compiler will select the appropriate architecture for your constraints.
However, you may force Design Compiler to use one of the architectures described in this table.
For more details, please refer to the DesignWare Building Block IP User Guide.
January 17, 2005
Synopsys, Inc.
209