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DesignWare IP Family
Arith
DW02_mult
Multiplier
a. During synthesis, Design Compiler will select the appropriate architecture for your constraints.
However, you may force Design Compiler to use one of the architectures described in this table.
For more details, please refer to the DesignWare Building Block IP User Guide.
c. In most cases, the wall implementation generates faster and smaller circuits for medium- to
large-sized multipliers.
d. Automatically selects Booth-recoding or non-Booth-recoding, depending on constraints.
e. This architecture is specially generated using Module Compiler technology. It is normally used as
a replacement for, rather than in conjunction with, the HDL architectures available for the same
DesignWare part. To use this architecture during synthesis, the dc_shell-t variable
dw_prefer_mc_inside must be set to ‘true’. From the DC 2004.12 release onward, the MC
architectures are not available by default. For more information, refer to the DesignWare Building
Block IP Users Guide.
f. This delay-optimized Booth Wallace architecture is generated using Datapath generator
technology DW “gensh.” This is ON by default in Design Compiler flow. The DC variable
‘synlib_enable_dpgen’ must be set to 'true' (the default) to make use of this Datapath technology.
January 17, 2005
Synopsys, Inc.
87
DWL Sythesizable IP
b. In cases where A_width+B_width ≤41, the nbw implementation generates a non-Booth recoded
Wallace-tree multiplier. For multipliers having products larger than 41 bits (such as,
A_width+B_width > 41) the nbw implementation produces a Booth-recoded multiplier identical to
the wall implementation.