Download DesignWare IP Family Reference Guide

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DesignWare IP Family
dwc_pci_express_dm
PCI Express RC/EP Dual Mode Synthesizable Core
Configurable BAR filtering, I/O
filtering, and configuration filtering
Programmable completion timeout
Supports up to three independent
client interfaces for transmitting TLPs
Access to configuration space
registers and external application
registers through local bus controller
Automatic generation of Completions
for devices that require only simple
access to an application register block
(EP mode)
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Automatic generation of Completions
for Requests that require Unsupported
Request (UR) or Completer Abort
(CA) responses (RC mode)
Selectable arbitration mechanism for
transmit interfaces, or use an external
arbiter
Supports expansion ROM
Implements parity checking on
transmit buses, memory buses, and
internal data buses (optional)
More information is available at:
http://www.synopsys.com/products/designware/pciexpress.html
DW Cores
June 2009
Synopsys, Inc.
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