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DesignWare IP Family
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r es
dwc_usb2_hsotg_phy
USB 2.0 Hi-Speed OTG PHY
dwc_usb2_hsotg_phy
USB 2.0 Hi-Speed OTG PHY
The Synopsys DesignWare Hi-Speed USB 2.0 On-The-Go (HS OTG) PHY is a complete
mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip,
USB 2.0 integration in OTG applications. The USB 2.0 OTG PHY includes all the
required logical, geometric, and physical design files to implement USB 2.0 Hi-Speed
OTG capability in a system-on-chip (SoC) design and to manufacture it in the designated
foundry. The USB 2.0 OTG PHY is available in 90-nanometer (nm), 130-nm, and 180-nm
CMOS digital logic processes.
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Complete mixed-signal physical layer
(PHY) for single-chip USB 2.0 OTG
applications
USB 2.0 Transceiver Macrocell
Interface (UTMI+ Level 3)
specification
8-bit interface at 60-MHz operation
and 16-bit interface at 30-MHz
operation
Hi-Speed (480 Mbps), Full-Speed (12
Mbps), and Low-Speed (1.5 Mbps)
operation is compliant to the USB
OTG Supplement
Supports all OTG features, including
Host Negotiation Protocol (HNP) and
Session Request Protocol (SRP)
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Synopsys, Inc.
Designed for rapid integration with
Synopsys’s HS USB 2.0 OTG
controller
Designed for minimal power
dissipation for low-power and
bus-powered devices
Verified in 90-nm, 130-nm, and
180-nm silicon
Based on Synopsys’s USB
Implementers Forum certified HS
USB 2.0 PHY architecture
June 2009