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TIMERS
10.2.2
Load/Store Access Latency for Timer Registers
As with all other load accesses from internal memory-mapped registers, a load instruction that
accesses a timer register has a latency of one internal processor cycle. With one exception, a store
access to a timer register completes and all state changes take effect before the next instruction
begins execution. The exception to this is when disabling a timer. Latency associated with the
disabling action is such that a timer interrupt may be posted immediately after the disabling
instruction completes. This can occur when the timer is near zero as the store to TMRx occurs. In
this case, the timer interrupt is posted immediately after the store to TMRx completes and before
the next instruction can execute. Table 10-5 summarizes the timer access and response timings.
Refer also to the individual register descriptions for details.
Note that the processor may delay the actual issuing of the load or store operation due to previous
instruction activity and resource availability of processor functional units.
The processor ensures that the TMRx.tc bit is cleared within one bus clock after a load or store
instruction accesses TMRx.
Table 10-5. Timer Responses to Register Bit Settings (Sheet 1 of 2)
Name
(TMRx.tc)
Terminal Count
Bit 0
Status
Action
READ
Timer clears this bit when user software accesses TMRx. This bit can
be set 1 bus clock later. The timer sets this bit within 1 bus clock of
TCRx reaching zero when TMRx.reload=0.
Timer clears this bit within 1 bus clock after the software accesses
WRITE TMRx. The timer ignores any value specified for TMRx.tc in a write
request.
(TMRx.enable)
READ
Bit is available 1 bus clock after executing a read instruction from
TMRx.
Timer Enable
Bit 1
WRITE
Writing a ‘1’ enables the bus clock to decrement TCRx within 1 bus
clock after executing a store instruction to TMRx.
(TMRx.reload)
READ
Bit is available 1 bus clock after executing a read instruction from
TMRx.
Timer Auto
Reload Enable
Bit 2
Writing a ‘1’ enables the reload capability within 1 bus clock after the
WRITE store instruction to TMRx has executed. The timer loads TRRx data
into TCRx and decrements this value during the next bus clock cycle.
10-9
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