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Load and store operations are assumed to be weakly ordered on the MPC7410. In
general, the load/store unit (LSU) can perform load operations that occur later in
the program ahead of store operations, even when the access is caching-inhibited
or when data cache is disabled. Any load followed by any store is performed in
order. See Section 3.4.4.2, “Sequential Consistency of Memory Accesses,” for
more information.
Split the second paragraph into two and add Table 3-8. The second paragraph,
Table 3-8, and the third paragraph should read as follows:
The MPC7410 achieves sequential consistency by operating a single pipeline to
the cache/MMU. All memory accesses are presented to the MMU in exact
program order and, therefore, exceptions are determined in order. Table 3-8
describes load/store ordering.
3.4.4.2, 3-31
Table 3-8. MPC7410 Load/Store Ordering
WIMG1
Store-Store
Ordered
Load-Load
Ordered
Store-Load
Ordered
Load-Store
Ordered
Caching-inhibited, guarded
01x1
Yes
Yes
Requires eieio
Yes
Caching-inhibited, non-guarded
01x0
Yes
Yes
Requires sync
Yes
Write-through, guarded
10x1
Yes
Yes
Requires sync
Yes
Write-through, non-guarded
10x0
Yes
Requires eieio
Requires sync
Yes
Write-back, coherency-required
001x
Requires eieio
Requires eieio
Requires sync
Yes
Write-back,
coherency-not-required
000x
Requires eieio
Requires eieio
Requires sync
Yes
Cache/Memory
Access Attributes
1
The PowerPC architecture states that combinations where WIMG = 11xx are not supported.
3.4.4.3, 3-31
3.7.2, 3-50
Loads are allowed to bypass stores once exception checking has been performed
for the store, but data dependency checking is handled in the load/store unit so that
a load will not bypass a store with an address match. Newer caching-allowed loads
can bypass older caching-allowed loads only if the two loads are to different
32-byte address granules. Newer caching-allowed write-back stores can bypass
older caching-allowed write-back stores if they do not store to overlapping bytes
of data.
Replace the first paragraph with the following:
Unlike previous PowerPC microprocessor implementations, the MPC7410 does
reorder cache-inhibited memory accesses and write-through, guarded memory
accesses. As shown in Table 3-8, certain memory accesses require an eieio or a
sync instruction to ensure ordering. These instructions are used to enforce storage
ordering.”
After the first paragraph, add Figure 3-35 and the following paragraph:
MPC7410/MPC7400 RISC Microprocessor Reference Manual, Rev. 2
C-4
Freescale Semiconductor