Download MPC7410/MPC7400 RISC Microprocessor Reference Manual

VFPU execution timing, 6-33
VSIU execution timing, 6-33
branch instruction latencies, 6-39
CR execution latencies, 6-40
examples
cache hit, 6-13
cache miss, 6-16
execution unit, 6-22
FPU execution latencies, 6-43
instruction flow, 1-8, 6-9
IU execution latencies, 6-41
LSU execution latencies, 6-44
memory coherency and the cache, 6-35
memory performance considerations, 6-35
overview, 1-8, 1-36, 6-3
terminology, 6-2
Instructions
addressing modes, 2-44
AltiVec
cache management, 2-92
instruction set, 7-4
transient instructions, 7-4
user-level instructions, 2-92
AltiVec instructions
execution latency, 6-46
overview, 1-30
boundedly undefined, 2-42
branch, A-56
address calculation, 2-64
branch instruction latencies, 6-39
branch instructions, 6-10, 6-23, 6-24
cache
management instructions, 2-92, 7-5, A-57
cache control instructions, 3-38
classes of instructions, 2-42
condition register logical, 2-65, A-56
condition register logical execution latencies, 6-40
context synchronization, 2-45
defined instruction class, 2-42
effective address calculation, 2-44
exceptions, 2-49
execution
synchronization, 2-48
external control, 2-73, A-58, A-61
floating-point
arithmetic, 2-54, A-51
compare, 2-55, A-52
estimate instructions, A-61
FPSCR instructions, A-53
load instructions, A-55
move, 2-56
move instructions, A-56
multiply-add, 2-54, A-51
rounding and conversion, 2-55, A-52
status and control register, 2-55
store instructions, A-55
floating-point instructions execution latencies, 6-43
flow
control, 2-88
illegal instruction class, 2-43
implementation-specific instructions, 1-30
instruction cache throttling, 10-10
instruction flow diagram, 6-11
instruction serialization, 6-21
instruction timing, 6-33
instructions not implemented, B-1
integer
arithmetic, 2-50, 2-79, A-49
compare, 2-51, A-49
load, A-53
load/store multiple, 2-60, A-54
load/store string, A-54
load/store with byte reverse, A-54
logical, 2-52, 2-79, A-50
rotate and shift, 2-52, A-50
store, 2-58, A-54
integer instruction execution latencies, 6-41
isync, 4-13
latency summary, 6-39
load and store
address generation
floating-point, 2-61
integer, 2-57
byte reverse instructions, 2-60, A-54
execution latencies, 6-44
floating-point load, A-55
floating-point move, 2-56, A-56
floating-point store, 2-62, A-55
indirect integer load, 2-57
integer
load, A-53
multiple, 2-60
store, 2-58, A-54
memory synchronization, 2-68, 2-69, A-55
misalignment handling, 2-56
multiple instructions, A-54
string instructions, 2-60, A-54
vector load, 2-86
LRU, 2-92
memory control instructions, 2-70, 2-77
memory synchronization instructions, 2-68, 2-69, A-55
move to/from VSCR register, 2-91
PowerPC
instruction list by functional categories, A-49
MPC7410/MPC7400 RISC Microprocessor Reference Manual, Rev. 2
Freescale Semiconductor
Index-7