Download MPC7410/MPC7400 RISC Microprocessor Reference Manual

Status (S0)
Status (S1)
Status (S2)
Status (S3)
F-Bit
Status (S0)
Status (S1)
Status (S2)
Status (S3)
F-Bit
4096 Sets
Way 0
Address Tag 0
Status (S0)
Status (S1)
Status (S2)
Status (S3)
F-Bit
Way 1
Address Tag 1
Status (S0)
Status (S1)
Status (S2)
Status (S3)
F-Bit
1, 2, or 4 Status Fields
Depends on Size of Cache
M
S
V
Figure 0-1. Figure 3-35. L2 Cache Controller Tag Organization
Physical address bits PA[13:24] provide the index to select a cache set. The tags
consist of physical address bits PA[0:12]. Physical address bits A[25:31] locate a
byte within the selected block.
3.7.3.7, 3-54
Add the following paragraph as the first step for performing a global invalidation
of the L2 cache:
1. Prefetch the code that monitors L2CR[L2IP] (step 5) into the L1 instruction cache. The L2IP
monitor code must be resident in the L1 instruction cache before the L2CR[L2I] bit is set (step 4).
Otherwise the global invalidate operation will prevent the fetching of the L2IP monitor code from
memory until after the invalidate has completed and the L2IP monitor code will never see the L2IP
bit set.
3.7.3.7, 3-54
In the first sentence of step 4, replace ‘L2CR[L2P]’ with ‘L2CR[L2IP].’ The
sentence should read as follows:
2. Monitor the L2CR[L2IP] bit to determine when the global invalidation operation is completed
(indicated by the clearing of L2CR[L2IP]).
3.7.6.2, 3-62
Add the following sentence at the beginning of the only paragraph:
The L2 cache uses a least-recently used (LRU) replacement algorithm.
3.7.9, 3-65
Add the following sentence at the end of the last paragraph (first paragraph on the
page):
Note that due to the influence of L2TS on the replacement algorithm, it is
necessary to initialize an address range that is twice (2X) the physical L2 cache
size and perform testing on the second half of that address range.
3.7.9.2, 3-65
Add the following sentence after the first sentence of step 4:
The range of addresses must be twice the physical L2 cache size.
Replace the second sentence of step 6 as follows:
MPC7410/MPC7400 RISC Microprocessor Reference Manual, Rev. 2
Freescale Semiconductor
C-5