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Download virtual-machine extensions (VMX)
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INDEX introduction to, 2-5, 2-6, 2-7 layout of, 6-14 referencing of TSS descriptor, 6-20 Task management, 7-1 data structures, 7-4 mechanism, description of, 7-3 Task register, 3-21 description of, 2-17, 7-1, 7-9 IA-32e mode, 2-17 initializing, 9-14 introduction to, 2-9 Task switching description of, 7-3 exception condition, 16-13 operation, 7-13 preventing recursive task switching, 7-18 saving MMX state on, 12-5 saving SSE/SSE2/SSE3 state on task or context switches, 13-9 T (debug trap) flag, 7-6 Tasks address space, 7-19 description of, 7-1 exception-handler task, 6-16 executing, 7-3 Intel 286 processor tasks, 19-51 interrupt-handler task, 6-16 interrupts and exceptions, 6-20 linking, 7-16 logical address space, 7-20 management, 7-1 mapping linear and physical address space, 7-19 restart following an exception or interrupt, 6-7 state (context), 7-2, 7-3 structure, 7-1 switching, 7-3 task management data structures, 7-4 TF (trap) flag, EFLAGS register, 2-12, 6-19, 16-12, 16-15, 16-39, 16-42, 16-44, 16-47, 17-6, 17-29, 26-14 Thermal monitoring advanced power management, 14-9 automatic, 14-12 automatic thermal monitoring, 14-10 catastrophic shutdown detector, 14-10, 14-12 clock-modulation bits, 14-17 C-state, 14-9 detection of facilities, 14-18 Enhanced Intel SpeedStep Technology, 14-1 IA32_APERF MSR, 14-2 IA32_MPERF MSR, 14-2 IA32_THERM_INTERRUPT MSR, 14-19 IA32_THERM_STATUS MSR, 14-19 interrupt enable/disable flags, 14-15 interrupt mechanisms, 14-11 MWAIT extensions for, 14-9 on die sensors, 14-11, 14-19 overview of, 14-1, 14-10 performance state transitions, 14-14 sensor interrupt, 10-2 setting thermal thresholds, 14-19 software controlled clock modulation, 14-11, 14-16 status flags, 14-14 status information, 14-14, 14-16 stop clock mechanism, 14-11 thermal monitor 1 (TM1), 14-12 thermal monitor 2 (TM2), 14-12 TM flag, CPUID instruction, 14-18 Thermal status bit, 14-19, 14-24 Thermal status log bit, 14-19, 14-24 Thermal threshold #1 log, 14-20, 14-25 Thermal threshold #1 status, 14-20, 14-25 Thermal threshold #2 log, 14-21, 14-25 Thermal threshold #2 status, 14-21, 14-25 THERMTRIP# interrupt enable bit, 14-22, 14-26 thread timeout indicator, E-5, E-11, E-15, E-18 Threshold #1 interrupt enable bit, 14-23, 14-27 Threshold #1 value, 14-22, 14-26 Threshold #2 interrupt enable, 14-23, 14-27 Threshold #2 value, 14-23, 14-27 TI (table indicator) flag, segment selector, 3-10 Timer, local APIC, 10-22 Time-stamp counter counting clockticks, 30-96 description of, 16-49 IA32_TIME_STAMP_COUNTER MSR, 16-49 RDTSC instruction, 16-49 reading, 2-32 software drivers for, 30-118 TSC flag, 16-49 TSD flag, 16-49 TLBs description of, 11-1, 11-6 flushing, 11-29 invalidating (flushing), 2-31 relationship to PGE flag, 19-26 relationship to PSE flag, 11-29 virtual TLBs, 28-5 TM1 and TM2 See: thermal monitoring, 14-12 TMR Trigger Mode Register, 10-45, 10-56, 10-60, 10-68 TMR (Trigger Mode Register), local APIC, 10-43 TPR Task Priority Register, 10-55, 10-60 TR (trace message enable) flag DEBUGCTLMSR MSR, 16-15, 16-39, 16-42, 16-45, 16-47 Trace cache, 11-6 Transcendental instruction accuracy, 19-10, 19-20 Translation lookaside buffer (see TLB) Trap gates difference between interrupt and trap gates, 6-19 Vol. 3B Index -23
