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PERFORMANCE MONITORING ware. Figure 30-4 shows the layout of IA32_PERF_GLOBAL_STATUS. A value of 1 in bits 0, 1, 32 through 34 indicates a counter overflow condition has occurred in the associated counter. When a performance counter is configured for PEBS, overflow condition in the counter generates a performance-monitoring interrupt signaling a PEBS event. On a PEBS event, the processor stores data records into the buffer area (see Section 18.15.5), clears the counter overflow status., and sets the “OvfBuffer” bit in IA32_PERF_GLOBAL_STATUS. 63 62 35 34 33 32 31 2 1 0 CondChgd OvfBuffer IA32_FIXED_CTR2 Overflow IA32_FIXED_CTR1 Overflow IA32_FIXED_CTR0 Overflow IA32_PMC1 Overflow IA32_PMC0 Overflow Reserved Figure 30-4. Layout of IA32_PERF_GLOBAL_STATUS MSR IA32_PERF_GLOBAL_OVF_CTL MSR allows software to clear overflow indicator(s) of any general-purpose or fixed-function counters via a single WRMSR. Software should clear overflow indications when • Setting up new values in the event select and/or UMASK field for counting or sampling • • Reloading counter values to continue sampling Disabling event counting or sampling. The layout of IA32_PERF_GLOBAL_OVF_CTL is shown in Figure 30-5. Vol. 3B 30-9
