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Download virtual-machine extensions (VMX)
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VM EXITS BOUND, and UD2); external interrupts that occur while the “acknowledge interrupt on exit” VM-exit control is 1; and non-maskable interrupts (NMIs). Such VM exits include those that occur on an attempt at a task switch that causes an exception before generating the VM exit due to the task switch that causes the VM exit. The following items detail the use of these fields: • VM-exit interruption information (format given in Table 21-14). The following items detail how this field is established for VM exits due to these events: — For an exception, bits 7:0 receive the exception vector (at most 31). For an NMI, bits 7:0 are set to 2. For an external interrupt, bits 7:0 receive the interrupt number. — Bits 10:8 are set to 0 (external interrupt), 2 (non-maskable interrupt), 3 (hardware exception), or 6 (software exception). Hardware exceptions comprise all exceptions except breakpoint exceptions (#BP; generated by INT3) and overflow exceptions (#OF; generated by INTO); these are software exceptions. BOUND-range exceeded exceptions (#BR; generated by BOUND) and invalid opcode exceptions (#UD) generated by UD2 are hardware exceptions. — Bit 11 is set to 1 if the VM exit is caused by a hardware exception that would have delivered an error code on the stack. This bit is always 0 if the VM exit occurred while the logical processor was in real-address mode (CR0.PE=0).1 If bit 11 is set to 1, the error code is placed in the VM-exit interruption error code (see below). — Bit 12 is undefined in any of the following cases: • If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs” VM-execution control is 0. • If the VM exit sets the valid bit in the IDT-vectoring information field (see Section 24.2.3). • If the VM exit is due to a double fault (the interruption type is hardware exception and the vector is 8). Otherwise, bit 12 is defined as follows: • If the “virtual NMIs” VM-execution control is 0, the VM exit is due to a fault on the IRET instruction (other than a debug exception for an instruction breakpoint), and blocking by NMI (see Table 21-3) was in effect before execution of IRET, bit 12 is set to 1. • If the “virtual NMIs” VM-execution control is 1, the VM exit is due to a fault on the IRET instruction (other than a debug exception for an 1. If the capability MSR IA32_VMX_CR0_FIXED0 reports that CR0.PE must be 1 in VMX operation, a logical processor cannot be in real-address mode unless the “unrestricted guest” VM-execution control and bit 31 of the primary processor-based VM-execution controls are both 1. 24-14 Vol. 3B
