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MODEL-SPECIFIC REGISTERS (MSRS) Table B-13. MSRs in the Pentium 4 and Intel Xeon Processors (Contd.) Register Address Hex 1A0H Register Name Fields and Flags Dec 416 IA32_MISC_ENABLE Model Availability Shared/ Unique1 3, Shared For Family F, Model 3 processors: When read, specifies the value of the target TM2 transition last written. When set, it sets the next target value for TM2 transition. 4, 6 Shared For Family F, Model 4 and Model 6 processors: When read, specifies the value of the target TM2 transition last written. Writes may cause #GP exceptions. 0, 1, 2, 3, 4, 6 Shared Enable Miscellaneous Processor Features. (R/W) Bit Description 0 Fast-Strings Enable. see Table B-2 1 Reserved. 2 x87 FPU Fopcode Compatibility Mode Enable. 3 Thermal Monitor 1 Enable. See Section 14.5.2, “Thermal Monitor.” and see Table B-2. 4 Split-Lock Disable. When set, the bit causes an #AC exception to be issued instead of a split-lock cycle. Operating systems that set this bit must align system structures to avoid split-lock scenarios. When the bit is clear (default), normal split-locks are issued to the bus. This debug feature is specific to the Pentium 4 processor. 5 Reserved. Vol. 3B B-179
