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MODEL-SPECIFIC REGISTERS (MSRS) Certain bit field position may be related to the maximum physical address width, the value of which is expressed as “MAXPHYWID“ in Table B-2. “MAXPHYWID“ is reported by CPUID.8000_0008H leaf. MSR address range between 40000000H - 400000FFH is marked as a specially reserved range. All existing and future processors will not implement any features using any MSR in this range. Table B-2. IA-32 Architectural MSRs Register Address Hex Decimal Architectural MSR Name and bit fields (Former MSR Name) MSR/Bit Description Introduced as Architectural MSR 0H 0 IA32_P5_MC_ADDR (P5_MC_ADDR) See Appendix B.12, “MSRs in Pentium Processors.” Pentium Processor (05_01H) 1H 1 IA32_P5_MC_TYPE (P5_MC_TYPE) See Appendix B.12, “MSRs in Pentium Processors.” DF_DM = 05_01H 6H 6 IA32_MONITOR_FILTER_S IZE See Section 8.10.5, “Monitor/Mwait Address Range Determination.” 0F_03H 10H 16 IA32_TIME_STAMP_ COUNTER (TSC) See Section 16.12, “TimeStamp Counter.” 05_01H 17H 23 IA32_PLATFORM_ID (MSR_PLATFORM_ID ) Platform ID. (RO) The operating system can use this MSR to determine “slot” information for the processor and the proper microcode update to load. 06_01H 49:0 Reserved. 52:50 Platform Id. (RO) Contains information concerning the intended platform for the processor. 52 0 0 0 0 1 1 1 1 63:53 51 0 0 1 1 0 0 1 1 50 0 1 0 1 0 1 0 1 Processor Flag 0 Processor Flag 1 Processor Flag 2 Processor Flag 3 Processor Flag 4 Processor Flag 5 Processor Flag 6 Processor Flag 7 Reserved. Vol. 3B B-3
