1
Download virtual-machine extensions (VMX)
Transcript
VMX SUPPORT FOR ADDRESS TRANSLATION 25.2.3.1 EPT Misconfigurations AN EPT misconfiguration occurs if any of the following is identified while translating a guest-physical address: • The value of bits 2:0 of an EPT paging-structure entry is either 010b (write-only) or 110b (write/execute). • The value of bits 2:0 of an EPT paging-structure entry is 100b (execute-only) and this value is not supported by the logical processor. Software should read the VMX capability MSR IA32_VMX_EPT_VPID_CAP to determine whether this value is supported (see Appendix G.10). • The value of bits 2:0 of an EPT paging-structure entry is not 000b (the entry is present) and one of the following holds: — A reserved bit is set. This includes the setting of a bit in the range 51:12 that is beyond the logical processor’s physical-address width.1 See Section 25.2.2 for details of which bits are reserved in which EPT paging-structure entries. — The entry is the last one used to translate a guest physical address (either an EPT PDE with bit 7 set to 1 or an EPT PTE) and the value of bits 5:3 (EPT memory type) is 2, 3, or 7 (these values are reserved). EPT misconfigurations result when an EPT paging-structure entry is configured with settings reserved for future functionality. Software developers should be aware that such settings may be used in the future and that an EPT paging-structure entry that causes an EPT misconfiguration on one processor might not do so in the future. 25.2.3.2 EPT Violations An EPT violation may occur during an access using a guest-physical address whose translation does not cause an EPT misconfiguration. An EPT violation occurs in any of the following situations: • Translation of the guest-physical address encounters an EPT paging-structure entry that is not present (see Section 25.2.2). • The access is a data read and bit 0 was clear in any of the EPT paging-structure entries used to translate the guest-physical address. Reads by the logical processor of guest paging structures to translate a linear address are considered to be data reads. • The access is a data write and bit 1 was clear in any of the EPT paging-structure entries used to translate the guest-physical address. Writes by the logical processor to guest paging structures to update accessed and dirty flags are considered to be data writes. • The access is an instruction fetch and bit 2 was clear in any of the EPT pagingstructure entries used to translate the guest-physical address. 1. Software can determine a processor’s physical-address width by executing CPUID with 80000008H in EAX. The physical-address width is returned in bits 7:0 of EAX. 25-12 Vol. 3B
