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Chapter 3: Using Digital Clock Managers (DCMs)
Table 3-35:
Clock Doubler Summary
DCM Output(s)
CLK2X
CLK2X180
Output Frequency
2 • F CLKIN
DCM Functional Unit
Delay-Locked Loop (DLL)
Feedback Required?
Yes
50% Duty Cycle?
Yes
Controlling Attributes
Spartan-3 FPGAs only:
DLL_FREQUENCY_MODE
On Spartan-3 FPGAs, the CLK2X and CLK2X180 outputs are only valid when
DLL_FREQUENCY_MODE = LOW.
CLKIN
Generally, the CLK2X and CLK2X180 outputs are only available up to a CLKIN of 167
MHz, primarily because the output frequency is limited to 334 MHz. On Spartan-3
FPGAs, the CLKIN frequency limits are determined by the DLL_FREQUENCY_MODE
attribute.
Spartan-3 Generation
FPGA Family
Minimum Frequency
Maximum Frequency
Spartan-3 FPGA
CLKIN_FREQ_DLL_LF_MIN
18 MHz
CLKIN_FREQ_DLL_LF_MAX
167 MHz
CLKIN_FREQ_DLL_MIN
5 MHz
Limited to half maximum
CLK2X frequency
-4: 155.5 MHz
-5: 167 MHz
CLKIN_FREQ_DLL_MIN
5 MHz
Limited to half maximum
CLK2X frequency
167 MHz
Spartan-3E FPGA
(Stepping 1)
Extended Spartan-3A
FPGA
CLK2X
CLK2X180
On Spartan-3 FPGAs, the CLK2X frequency limits are determined by the
DLL_FREQUENCY_MODE attribute.
Spartan-3 Generation
FPGA Family
Minimum Frequency
Maximum Frequency
CLKOUT_FREQ_2X_LF_MIN CLKOUT_FREQ_2X_LF_MAX
36 MHz
334 MHz
Spartan-3 FPGA
Spartan-3E FPGA
(Stepping 1)
Extended Spartan-3A
FPGA
CLKOUT_FREQ_2X_MIN
CLKOUT_FREQ_2X_MAX
10 MHz
-4: 311 MHz
-5: 334 MHz
CLKOUT_FREQ_2X_MIN
CLKOUT_FREQ_2X_MAX
10 MHz
334 MHz
Clock Divider (CLKDV)
The Clock Divider unit, summarized in Table 3-36, divides the incoming CLKIN frequency
by the value specified by the CLKDV_DIVIDE attribute, set at design time. The Clock
Divider unit is part of the DLL functional unit and requires a clock feedback path back to
CLKFB from either the CLK0 or CLK2X output.
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Spartan-3 Generation FPGA User Guide
UG331 (v1.5) January 21, 2009