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Chapter 2
Using Global Clock Resources
Summary
This chapter describes how to take advantage of the Spartan®-3 generation global clock
resources, including the dedicated clock inputs, buffers, and routing. The clocking
infrastructure provides a series of low-capacitance, low-skew interconnect lines wellsuited to carrying high-frequency signals throughout the FPGA, minimizing clock skew
and improving performance, and should be used for all clock signals. Third-party
synthesis tools, and Xilinx synthesis and implementation tools, automatically use these
resources for high-fanout clock signals.
This chapter focuses on the global clock resources found in all Spartan-3 generation
platforms, and the quadrant clock resources found in the Spartan-3E and Extended
Spartan-3A families. The clock routing can be used in conjunction with the DCMs, which
are discussed in more detail in Chapter 3, “Using Digital Clock Managers (DCMs).” For
information on the special clock inputs used for configuration (CCLK) and Boundary-Scan
(TCK), see UG332, Spartan-3 Generation Configuration User Guide.
Introduction
Each Spartan-3 generation FPGA device offers eight high-speed, low-skew global clock
resources to optimize performance. These resources are used automatically by the Xilinx
tools. Even if the clock rate is relatively slow, it is still important to use the global routing
resources to eliminate any potential for timing hazards. It is important to understand how
to define and best take advantage of these resources.
Global Clock Resource Differences between Spartan-3 Generation
Families
The Spartan-3E and Extended Spartan-3A family FPGAs have identical global clock
resources, with eight global clock inputs and an additional eight clocks on the left and right
sides of the device. The original Spartan-3 family offers only the eight global clock inputs.
Although the clock resources and routing are similar, there will be timing differences
between each platform and between different densities within a platform. This chapter
focuses on the architecture of the Spartan-3E and Extended Spartan-3A families. The
Spartan-3 family offers a simpler set of dedicated clock inputs and routing – for details, see
the Spartan-3 FPGA Family Data Sheet.
Spartan-3 Generation FPGA User Guide
UG331 (v1.5) January 21, 2009
www.xilinx.com
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